Introduction
Lithography is the art of printing patterns onto silicon — and the precision of that printing determines how small transistors can be, how many fit on a chip, and ultimately how fast and efficient that chip performs. For the past several years, Extreme Ultraviolet (EUV) lithography using ASML's NXE platform (Numerical Aperture 0.33) has been the defining tool of advanced semiconductor manufacturing at TSMC, Samsung, and Intel.
As of 2026, the next generation is entering production: High-NA EUV, with a Numerical Aperture of 0.55, implemented in ASML's EXE:5000 and EXE:5200 systems. This is not an incremental upgrade — it is a step-change in resolution capability that enables the printing of features below 10nm half-pitch, unlocking semiconductor scaling through the remainder of this decade and into the early 2030s.
It is worth being clear about where this is written from. I design robotics, UAV and industrial-automation systems, and the software that runs them. I have never operated a lithography scanner, and nothing here is a first-hand account of one — this is an engineer’s reading of the public record: ASML’s own disclosures, foundry roadmaps, and conference reporting.
The reason to write it from that position is that lithography sits at the top of a supply chain I sit at the bottom of. What a handful of machines in Veldhoven can print decides, several years later, which parts I can actually put in a bill of materials, at what price, and for how long I can keep buying them. That is a different question from “how small can a transistor get”, and it is the one I care about.
What follows is the physics of why numerical aperture matters, what High-NA delivers in practice, and how it differs from the current generation of EUV tools — and then, in the last section before the conclusion, what a machine builder should and should not conclude from any of it.
The Physics of Lithographic Resolution
Lithographic resolution — the minimum feature size that can be reliably printed — is governed by the Rayleigh criterion: R = k1 × (λ / NA), where λ is the wavelength of the illumination source, NA is the Numerical Aperture of the optical system, and k1 is a process-dependent factor reflecting the difficulty of the exposure.
Current EUV systems use λ = 13.5nm (extreme ultraviolet) and NA = 0.33. The minimum half-pitch they can print is approximately 13nm with optimized illumination conditions (low k1). This is the resolution capability that enables N3, N2, and Intel 18A nodes — the most advanced chips in production or near-production as of mid-2026.
High-NA EUV increases the NA from 0.33 to 0.55 — a 67% increase. Applying the Rayleigh criterion, this directly improves resolution by the same factor, enabling reliable printing at half-pitches approaching 8nm. This additional resolution headroom is what enables the next generation of sub-2nm nodes that chipmakers are planning for 2027–2030 introduction.
What Makes High-NA EUV Technically Different
Increasing NA in an optical system is not as simple as using a bigger lens. The optical physics become significantly more challenging at higher NA — anamorphic optics (optics with different magnification in X and Y directions) are required to manage the larger angles involved. ASML's High-NA EUV tools use a 4x magnification in one direction and 8x in the other (versus 4x isotropic in standard EUV), which requires significant changes to the mask (reticle) design for High-NA exposures.
The mirrors in the optical system must be manufactured to angstrom-level surface precision — even more demanding than the already extraordinary precision required for standard EUV optics. The illumination source (a 13.5nm plasma source based on tin droplet laser ablation) must also be upgraded for the higher etendue requirements of the 0.55 NA system.
The EXE:5000, ASML's first High-NA EUV production tool, is a physically massive machine — even larger than the already room-sized standard EUV systems. Each unit costs approximately $350–400 million, roughly double the cost of current EUV systems. This cost is justified only at the most advanced nodes where the resolution improvement is necessary to continue scaling.
Where High-NA EUV Is Being Deployed in 2026
Intel was the first chipmaker to receive and install a High-NA EUV system, with their EXE:5000 unit arriving at their Oregon fab in 2024 for process development. As of 2026, Intel is actively using High-NA EUV for process development targeting nodes beyond 18A — particularly for the most critical, most resolution-limited patterning layers.
TSMC received their first High-NA EUV tool in 2025 and is conducting process development for N2P and beyond. TSMC's N2 node (scheduled for volume production in 2025–2026) still uses standard 0.33 NA EUV for most critical layers, but High-NA is being evaluated for layers that would otherwise require multiple patterning passes with current tools.
Samsung is also engaged with ASML on High-NA EUV development, though their timeline for production deployment is less clearly defined compared to Intel and TSMC.
The Depth of Focus Challenge — The Critical Technical Trade-off
Higher NA improves resolution but reduces Depth of Focus (DoF). DoF — the vertical range over which the image is sufficiently sharp to expose the resist correctly — shrinks as NA increases. At 0.55 NA with 13.5nm wavelength, the DoF is significantly smaller than at 0.33 NA.
In practice, this means that the wafer flatness, resist film thickness, and focus control of the lithography system must all improve proportionally to take advantage of High-NA resolution without sacrificing process window. Wafer flatness specifications for High-NA EUV exposure are extremely demanding — nanometer-level height variation across the exposure field.
This is one of the key process engineering challenges that ASML, wafer suppliers, and chipmakers are collectively working to solve for High-NA EUV volume manufacturing. It is also why High-NA EUV will initially be used selectively — only for layers where its resolution benefit justifies the tighter process requirements — rather than replacing standard EUV across all layers at once.
High-NA EUV and the SMIC Lithography Debate
The question of what SMIC — China's leading semiconductor foundry, operating under strict US export controls that prevent access to advanced EUV tools — can achieve without EUV has been a major topic in the semiconductor industry through 2025–2026.
SemiAnalysis published analysis in June 2026 comparing SMIC's N+3 node metal pitch against Intel 18A, suggesting that SMIC has achieved tighter metal pitch than expected using multi-patterning techniques with older DUV (Deep Ultraviolet) lithography tools. This is a technically significant achievement — multi-patterning with ArF immersion DUV can extend resolution beyond what single-pass exposure achieves, though at significantly higher process complexity, lower throughput, and higher cost.
The analysis highlights that the real advantage of EUV (and High-NA EUV) is not just resolution, but economics. EUV achieves equivalent patterning in fewer process steps than multi-patterning DUV, resulting in higher throughput, better yield, and lower cost-per-wafer at equivalent resolution. High-NA EUV extends this economic advantage to patterns that would require even more DUV multi-patterning passes.
Implications for the Semiconductor Supply Chain and Industrial Electronics
For engineers and architects who design systems using advanced semiconductors, the High-NA EUV roadmap has several practical implications.
The chips enabled by High-NA EUV nodes (post-2027 timeframe) will deliver the next step-change in edge AI compute density and efficiency. This means the AI accelerators and inference processors used in industrial automation, robotics, and autonomous systems will see another capability jump in the 2028–2030 timeframe, enabling models that currently require data center hardware to run on embedded hardware.
The concentrated nature of High-NA EUV tooling — only ASML manufactures these systems, and only Intel, TSMC, and Samsung have them in 2026 — means that access to the most advanced semiconductor processes remains highly restricted geographically and economically. System designers should account for this in long-term supply chain planning.
The cost of High-NA EUV-enabled chips will be higher than equivalent chips on current nodes, at least initially. The economics improve as process maturity and yield increase, but system architects should expect premium pricing for the first generation of High-NA EUV products.
What this changes for engineers who buy chips rather than make them
The honest answer is: less than the headline suggests, and on a much longer timescale — but not nothing.
The first thing to internalise is that the leading edge is not where industrial and embedded parts live. The microcontrollers, motor-drive controllers and industrial SoCs that go into automation hardware are typically several generations behind the node being discussed here, and for good reasons: mature nodes are cheaper, better characterised, and — decisively for industrial work — available for years. A part with a ten-year lifecycle guarantee matters far more to a machine that has to run for a decade than a part with the best switching performance.
So the practical transmission mechanism is indirect. High-NA does not put a faster part in an automation cabinet next year. What it does is keep the economics of the leading edge moving, which over time pulls capacity and cost structure along behind it. The capability that shows up in an edge-AI module a few years from now is downstream of decisions being made in fabs now.
There is a design lesson in that lag, and it is one I hold to generally: never architect a machine around a part that only exists at the frontier. The frontier is where supply is tightest, prices are least predictable, and second sources do not exist. If a design only works with the newest available silicon, that is usually a sign the architecture is doing too little and the component is doing too much.
The way I approach this is to start from the system requirements and the failure modes, and select technology afterwards — not the reverse. A control loop that must close deterministically in a fixed window does not become correct because the processor got faster; it becomes correct because the timing and the failure behaviour were designed. Reading a lithography roadmap is useful for planning what will be procurable in three to five years. It is not a substitute for any of that work.
Conclusion
High-NA EUV is the tool that keeps semiconductor scaling economically viable through the end of this decade. ASML’s EXE:5000 and EXE:5200 systems provide the resolution headroom needed for post-2nm generations; the physics are demanding, the engineering is extraordinary, and the cost per tool is enormous — but the alternative is accepting the end of the scaling curve, which no chipmaker is willing to do.
Read from the machine side, it belongs in the same mental category as a foundry roadmap or a lifecycle notice: a signal about what will be available to design with in three to five years, and at what cost. That is genuinely worth tracking. It is not a reason to change anything about a system you are building this quarter.