Introduction
Every decade or so, the semiconductor industry makes a fundamental change to the transistor structure itself — not just shrinking an existing design, but adopting an entirely new architecture to overcome physical limits that the previous generation could not escape. The last major transition was from planar MOSFETs to FinFETs (also called Tri-Gate transistors), which Intel pioneered at 22nm in 2011 and which TSMC and Samsung adopted at 16/14nm. FinFETs enabled semiconductor scaling to continue for over a decade.
In 2026, the next transition is underway: Gate-All-Around (GAA) transistors — also called nanosheet FETs, nanowire FETs, or RibbonFETs (Intel's terminology). TSMC has deployed GAA nanosheet transistors in N2, their most advanced production node. Intel has deployed RibbonFETs in Intel 18A, targeting production in 2026. Samsung was first to market with GAA at 3nm (SF3E) in 2022.
Before the physics, a note on perspective. I build robotics, UAV and industrial-automation systems rather than semiconductors, and this article is analysis of published material from Intel, TSMC, Samsung and imec — not a first-hand account of process development. I have not fabricated a nanosheet transistor and will not pretend otherwise.
What I can offer is the downstream reading: a transistor architecture change is one of the few upstream events that eventually reaches the person specifying a part, because it moves the leakage and drive-current characteristics that decide how an embedded processor behaves when it is doing nothing — which, for a great deal of industrial and edge hardware, is most of the time.
What follows is the physics of why FinFETs ran out of road, how gate-all-around structures address it, what makes them hard to manufacture — and then an honest account of when and how any of it shows up in the parts an automation or robotics engineer can actually buy.
Why FinFETs Are Running Out of Headroom
FinFET — Fin Field-Effect Transistor — works by wrapping the gate around three sides of a thin silicon fin. This three-sided gate wrap gives much better electrostatic control over the channel compared to a planar gate (which only controls from one side), enabling lower leakage current and better switching performance as transistors scale to smaller dimensions.
The problem: as FinFETs scale to 3nm and below, the fin itself becomes so narrow — just a few nanometers wide — that it is extremely difficult to manufacture with acceptable uniformity and yield. Fin width variation directly causes transistor performance variation, and at sub-5nm fin widths, the lithographic and etch process control required to maintain tight variation is at the edge of what current tools can achieve.
Additionally, the fin height in FinFETs is fixed by the process — you cannot easily adjust it to change the drive current. Drive current (how much current a transistor can supply to charge/discharge the next stage) is a critical performance parameter. In FinFETs, the only way to increase drive current is to increase the number of fins per transistor — but each additional fin takes additional area, working against the density improvement that scaling is supposed to deliver.
These two constraints — process variation at small fin dimensions and the inflexibility of fin count for drive current tuning — are the walls that have pushed the industry toward Gate-All-Around.
How Gate-All-Around Transistors Work
In a GAA nanosheet transistor, instead of a fin, the channel consists of one or more horizontal silicon nanosheets — thin, flat ribbons of silicon stacked vertically. The gate material wraps completely around each nanosheet — on top, bottom, and both sides — providing full 360-degree electrostatic control over the channel.
This full wraparound gate provides superior electrostatic control compared to FinFET's three-sided gate, enabling lower threshold voltage, lower leakage, better short-channel behavior at small gate lengths, and higher drive current per unit area. The physics are fundamentally more favorable.
Critically, the width of each nanosheet can be controlled by the lithography step that defines it — unlike FinFET fin width, which is constrained by the fin pitch. This means the designer can tune the nanosheet width (and therefore the drive current) for each transistor type within the same process node. High-performance transistors use wider nanosheets for more drive current; low-power transistors use narrower nanosheets to minimize leakage. This is a significant new degree of freedom in transistor design that FinFETs do not provide.
Intel RibbonFET — The Implementation in Intel 18A
Intel's GAA implementation is called RibbonFET — named after the ribbon-like nanosheet channel structure. In Intel 18A, RibbonFETs are combined with PowerVia (backside power delivery) as the two key process innovations of the node.
Intel's RibbonFET uses stacked nanosheet ribbons, with the gate completely surrounding each ribbon. Intel has indicated that RibbonFET provides improved performance and power versus their previous FinFET-based nodes (Intel 7, Intel 4, Intel 3) at equivalent gate length — consistent with the physics advantages of the GAA structure.
The combination of RibbonFET and PowerVia in a single node is architecturally significant because the two innovations compound: GAA transistors improve transistor-level performance and density, while backside power delivery improves routing efficiency and supply voltage uniformity. Together, they represent a larger node-over-node performance and density step than either alone would provide.
TSMC N2 — Nanosheet GAA at Volume Scale
TSMC's N2 (2nm generation) deploys nanosheet GAA transistors at volume manufacturing scale, targeting high-volume production for Apple silicon and other leading-edge SoC customers in 2025–2026. TSMC's N2 is the first TSMC node to use GAA, transitioning from their N3 generation (still FinFET-based) to GAA for the first time.
TSMC reports approximately 10–15% performance improvement at the same power, or equivalent performance at 25–30% lower power, versus N3B — consistent with the GAA physics advantage. Transistor density on N2 is approximately 1.15x higher than N3B, delivering continued Moore's Law scaling.
TSMC's N2P (performance variant) and N2X (extreme performance variant) will further optimize the GAA nanosheet process for higher frequency applications, with N2P expected to add 5% additional performance over baseline N2 through gate length and nanosheet width optimization.
Manufacturing Challenges — Why GAA Is Hard to Make
The physics advantages of GAA come with significant manufacturing complexity. The nanosheet stack — multiple silicon nanosheets separated by sacrificial silicon germanium (SiGe) layers — must be grown epitaxially with precise thickness control for each layer. The SiGe sacrificial layers are then selectively etched away to release the nanosheets and create the cavity for gate dielectric deposition — a process step called the "release etch" that requires extraordinary selectivity between Si and SiGe.
Gate dielectric deposition then must conformally coat all four surfaces of each nanosheet simultaneously — ensuring uniform high-k dielectric thickness on the top, bottom, and sides of each nanosheet in the stack. This is a far more demanding deposition challenge than coating the three surfaces of a FinFET fin.
Source and drain contacts in GAA also require precision epitaxial growth in the regions between nanosheets — the inner spacers that electrically isolate the source/drain from the gate metal must be formed with nanometer-level precision to avoid leakage or increased parasitic capacitance.
These process complexities mean that GAA yield ramp takes longer than FinFET yield ramp for equivalent investments. TSMC and Intel have both invested years of process development in their GAA implementations before entering production — the physics may be more favorable, but the manufacturing is significantly more demanding.
What GAA Means for Chip Performance in Real Systems
For electronics engineers and system architects, the practical implications of GAA transistors arriving in production nodes in 2026 are concrete and significant.
AI accelerator chips — the processors that run neural network inference in cloud data centers and, increasingly, at the edge — benefit most dramatically from GAA. The combination of higher drive current, lower leakage, and improved density translates directly to more TOPS (Tera-Operations Per Second) per watt. For edge AI applications in industrial automation and robotics, this means more capable inference models running in the same thermal budget.
High-performance embedded processors on GAA nodes will see clock frequency improvements of 10–15% at equivalent power, or equivalent frequency at 25–30% lower power. For battery-operated or thermally-constrained embedded systems — portable robotics, wireless IoT sensors, autonomous mobile robots — the power reduction is the more important parameter.
SRAM bit cell density improvements on GAA nodes also contribute to chip area reduction, meaning SoCs can integrate more on-chip cache and memory in smaller die area, reducing memory bandwidth bottlenecks for AI workloads.
Reading a transistor change from the machine side
Two things are worth separating here: what the architecture does electrically, and when it becomes relevant to a working design. They have very different timescales.
Electrically, the interesting consequence for embedded work is not peak performance — it is leakage. Better electrostatic control means the gate turns the channel off more completely, and off-state behaviour is what dominates the energy budget of a device that spends its life waiting: a sensor node sampling every few seconds, a monitoring device on a battery, an always-on edge processor idling between events. A part that leaks less at rest changes what is possible in that class of design far more than a part that computes faster under load.
The second useful property is that nanosheet width is a design variable. Being able to tune drive current per device by adjusting sheet width gives chip designers a knob that FinFET quantisation did not allow, which tends to produce libraries better matched to low-power operation rather than only to peak frequency. That is a favourable direction for embedded silicon.
Then the timescale. None of this reaches an industrial bill of materials soon. The parts that go into automation hardware sit generations behind the leading edge, and they sit there deliberately — mature nodes are cheaper, better characterised, and supported for the years a deployed machine needs. By the time gate-all-around appears in a microcontroller with a ten-year availability commitment, it will be unremarkable, and the interesting engineering will be elsewhere.
Which is roughly how I think it should be treated: as useful context for what will be procurable later, not as an input to a current design. My own sequence is to work from the system requirements and the failure modes first and choose components afterwards. A transistor roadmap tells you what the component menu will look like in a few years. It tells you nothing about whether your machine degrades safely when a sensor stops reporting — and that is the harder problem.
Conclusion
Gate-all-around is the most fundamental change to transistor structure since FinFETs arrived over a decade ago. The physics below roughly 3nm clearly favour it: better electrostatic control, tunable drive current through sheet width, and better short-channel behaviour. The manufacturing is materially harder — sheet formation, inner spacers and the work-function metal stack are all difficult — and both Intel and TSMC reaching production yields is the real news in it.
For anyone building machines rather than chips, the honest summary is that this is a genuine improvement arriving on a long fuse. The property to watch is leakage, because that is what changes the design space for always-on embedded hardware. The property not to plan around is availability, which will lag by years — and, for industrial work, should.